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PRELIMINARY
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
Features
* Supports bus operation up to 250 MHz * Available speed grades are 250, 200,167 MHz * Registered inputs and outputs for pipelined operation * 3.3V core power supply * 2.5V/3.3V I/O operation * Fast clock-to-output times -- 2.6 ns (for 250-MHz device) -- 3.2 ns (for 200-MHz device) -- 3.4 ns (for 167-MHz device) * Provide high-performance 3-1-1-1 access rate * User-selectable burst counter supporting Pentium(R) interleaved or linear burst sequences * Separate processor and controller address strobes * Synchronous self-timed writes * Asynchronous output enable * Single Cycle Chip Deselect * Offered in JEDEC-standard 100-pin TQFP, 165-Ball fBGA and 209-Ball fBGA packages * Also available in lead-free packages * IEEE 1149.1 JTAG-Compatible Boundary Scan * "ZZ" Sleep Mode Option Intel(R)
Functional Description[1]
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1,048,576 x 36, 2,097,152 x 18 and 524,288 x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.6 475 100 200 MHz 3.2 425 100 167 MHz 3.4 375 100 Unit ns mA mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Notes: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3, CE2 are for TQFP and 165 fBGA package only.
Cypress Semiconductor Corporation Document #: 38-05383 Rev. *B
*
3901 North First Street
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San Jose, CA 95134 * 408-943-2600 Revised January 31, 2005
PRELIMINARY
Logic Block Diagram - CY7C1440AV33 (1 Mbit x 36)
A0, A1, A
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
ADDRESS REGISTER
2
A[1:0]
MODE ADV CLK
Q1
ADSC ADSP
BWD DQD ,DQPD BYTE WRITE REGISTER DQC ,DQPC BYTE WRITE REGISTER DQB ,DQPB BYTE WRITE REGISTER DQA ,DQPA BYTE WRITE REGISTER
BURST COUNTER CLR AND Q0 LOGIC
DQD ,DQPD BYTE WRITE DRIVER DQC ,DQPC BYTE WRITE DRIVER DQB ,DQPB BYTE WRITE DRIVER DQA ,DQPA BYTE WRITE DRIVER
BWC
MEMORY ARRAY
SENSE AMPS
OUTPUT REGISTERS
OUTPUT BUFFERS E
BWB
DQs DQPA DQPB DQPC DQPD
BWA BWE
GW CE1 CE2 CE3 OE
ENABLE REGISTER
PIPELINED ENABLE
INPUT REGISTERS
ZZ
SLEEP CONTROL
Logic Block Diagram - CY7C1442AV33 (2 Mbit x 18)
A0, A1, A
MODE
ADDRESS REGISTER
2 A[1:0]
ADV CLK
BURST Q1 COUNTER AND LOGIC CLR Q0
ADSC
ADSP DQB,DQPB WRITE REGISTER DQB,DQPB WRITE DRIVER MEMORY ARRAY BWA BWE GW CE1 CE2 CE3 OE ENABLE REGISTER DQA,DQPA WRITE REGISTER DQA,DQPA WRITE DRIVER SENSE AMPS
BWB
OUTPUT REGISTERS
OUTPUT BUFFERS
E
DQs DQPA DQPB
PIPELINED ENABLE
INPUT REGISTERS
ZZ
SLEEP CONTROL
Document #: 38-05383 Rev. *B
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PRELIMINARY
Logic Block Diagram - CY7C1446AV33 (512K x 72)
A0, A1,A
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
ADDRESS REGISTER
A[1:0]
MODE ADV CLK Q1 BINARY COUNTER CLR Q0
ADSC ADSP
BWH
DQH, DQPH WRITE DRIVER DQF, DQPF WRITE DRIVER DQF, DQPF WRITE DRIVER DQE, DQPE WRITE DRIVER DQD, DQPD WRITE DRIVER
DQH, DQPH WRITE DRIVER DQG, DQPG WRITE DRIVER DQF, DQPF WRITE DRIVER DQE, DQPE BYTE "a" WRITE DRIVER DQD, DQPD WRITE DRIVER DQC, DQPC WRITE DRIVER
SENSE AMPS
BWG
BWF
BWE
MEMORY ARRAY
BWD
BWC
DQC, DQPC WRITE DRIVER
OUTPUT REGISTERS
BWB
DQB, DQPB WRITE DRIVER
DQB, DQPB WRITE DRIVER DQA, DQPA WRITE DRIVER
OUTPUT BUFFERS E
BWA BWE GW CE1 CE2 CE3 OE
DQA, DQPA WRITE DRIVER
ENABLE REGISTER
PIPELINED ENABLE
INPUT REGISTERS
DQs DQPA DQPB DQPC DQPD DQPE DQPF DQPG DQPH
ZZ
SLEEP CONTROL
Document #: 38-05383 Rev. *B
Page 3 of 27
PRELIMINARY
Pin Configurations
100-pin TQFP Pinout
A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPC DQC DQc VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1440AV33 (1 Mbit x 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA
NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1442AV33 (2 Mbit x 18)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 NC / 72M A VSS VDD
MODE A A A A A1 A0 NC / 72M A VSS VDD
A A A A A A A A A
Document #: 38-05383 Rev. *B
A A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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PRELIMINARY
Pin Configurations (continued)
165-ball fBGA
CY7C1440AV33 (1 Mbit x 36)
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
1 A B C D E F G H J K L M N P R
NC / 288M NC DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE
2
A A NC DQC DQC DQC DQC NC DQD DQD DQD DQD NC NC / 72M A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
BWE GW
8
ADSC OE VSS VDD
9
ADV ADSP
10
A A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A
11
NC NC / 144M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
A
A
CY7C1442AV33 (2 Mbit x 18)
1 A B C D E F G H J K L M N P R
NC / 288M NC NC NC NC NC NC NC DQB DQB DQB DQB DQPB NC MODE
2
A A NC DQB DQB DQB DQB NC NC NC NC NC NC NC / 72M A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
BWE GW
8
ADSC OE
9
ADV ADSP
10
A A NC NC NC NC NC NC DQA DQA DQA DQA NC A A
11
A NC / 144M DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
A
A
Document #: 38-05383 Rev. *B
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PRELIMINARY
Pin Configurations (continued)
209-ball fBGA CY7C1446AV33 (512K x 72) 1 A B C D E F G H J K L M N P R T U V W 2 3
A BWSC BWSH VSS VDDQ VSS VDDQ VSS VDDQ CLK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
4
CE2 BWSG BWSD NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI
5
6
7
ADV A NC GW VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A
8
CE3 BWSB BWSE NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO
9
A BWSF BWSA VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS A A TCK
10
11
DQG DQG DQG DQG DQPG DQC DQC DQC DQC
NC
DQG DQG DQG DQG DQPC DQC DQC DQC DQC
NC
ADSP ADSC NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A BW CE1 OE VDD NC NC NC NC VSS NC NC NC ZZ VDD MODE A A1 A0
DQB DQB DQB DQB DQPF DQF DQF DQF DQF
NC
DQB DQB DQB DQB DQPB DQF DQF DQF DQF
NC
DQH DQH DQH DQH DQPD DQD DQD DQD DQD
DQH DQH DQH DQH DQPH DQD DQD DQD DQD
DQA DQA DQA DQA DQPA DQE DQE DQE DQE
DQA DQA DQA DQA DQPE DQE DQE DQE DQE
Pin Definitions
Name A0, A1, A I/O InputSynchronous InputSynchronous Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled active. A1: A0 are fed to the two-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK.
BWA, BWB, BWC, BWD, BWE, BWF, BWG, BWH GW
InputSynchronous InputSynchronous InputClock InputSynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded.
BWE CLK CE1
Document #: 38-05383 Rev. *B
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PRELIMINARY
Pin Definitions (continued)
Name CE2[2] I/O InputSynchronous InputSynchronous Description
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Not available for AJ package version. Not connected for BGA. Where referenced, CE3 is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ "sleep" Input, active HIGH. When asserted HIGH places the device in a non-time-critical "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. Power supply inputs to the core of the device. Ground for the core of the device. Ground for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP packages.
CE3[2]
OE
InputAsynchronous
ADV ADSP
InputSynchronous InputSynchronous
ADSC
InputSynchronous
ZZ
InputAsynchronous I/OSynchronous
DQs, DQPX
VDD VSS VSSQ VDDQ MODE
Power Supply Ground I/O Ground InputStatic JTAG serial output Synchronous
I/O Power Supply Power supply for the I/O circuitry.
TDO
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAGClock - - Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die No Connects. Not internally connected to the die. NC/72M, NC/144M and NC/288M are address expansion pins are not internally connected to the die.
TMS
TCK NC NC/72M, NC/144M, NC/288M
Document #: 38-05383 Rev. *B
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PRELIMINARY
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6ns (250-MHz device). The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486TM processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the Write signals (GW, BWE) are all deserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the Address Register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The Write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH, Document #: 38-05383 Rev. *B
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
then the Write operation is controlled by BWE and BWX signals. The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 provides Byte Write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWX) input, will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BWX) are asserted active to conduct a Write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to the DQs is written into the corresponding address location in the memory core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 provides a two-bit wraparound counter, fed by A1: A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering
Page 8 of 27
PRELIMINARY
the "sleep" mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
Interleaved Burst Address Table (MODE = Floating or VDD)
First Address A1: A0 00 01 10 11 First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00 Fourth Address A1: A0 11 00 01 10
Linear Burst Address Table (MODE = GND)
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ Active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 100 2tCYC Unit mA ns ns ns ns
Truth Table [3, 4, 5, 6, 7, 8]
Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Sleep Mode, Power Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst Add. Used None None None None None None External External External External External CE1 H L L L L X L L L L L CE2 X L X L X X H H H H H CE3 X X H X H X L L L L L ZZ L L L L L H L L L L L ADSP X L L H H X L L H H H ADSC L X X L L X X X L L L ADV X X X X X X X X X X X WRITE OE CLK X X X X X X X X L H H X X X X X X L H X L H DQ L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State X L-H L-H L-H Tri-State Q D Q
L-H Tri-State
L-H Tri-State
Notes: 3. X = "Don't Care." H = Logic HIGH, L = Logic LOW. 4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2. 7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05383 Rev. *B
Page 9 of 27
PRELIMINARY
Truth Table (continued)[3, 4, 5, 6, 7, 8]
Operation READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Add. Used Next Next Next Next Next Next Current Current Current Current Current Current CE1 X X H H X H X X H H X H CE2 X X X X X X X X X X X X CE3 X X X X X X X X X X X X ZZ L L L L L L L L L L L L ADSP H H X X H X H H X X H X ADSC H H H H H H H H H H H H ADV L L L L L L H H H H H H
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
WRITE OE CLK H H H H L L H H H H L L L H L H X X L H L H X X L-H L-H L-H L-H L-H L-H L-H L-H
DQ Q Q D D Q Q D D
L-H Tri-State L-H Tri-State
L-H Tri-State L-H Tri-State
Truth Table for Read/Write[5,9,10]
Function (CY7C1440AV33) Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write Bytes B, A Write Byte C - (DQC and DQPC) Write Bytes C, A Write Bytes C, B Write Bytes C, B, A Write Byte D - (DQD and DQPD) Write Bytes D, A Write Bytes D, B Write Bytes D, B, A Write Bytes D, C Write Bytes D, C, A Write Bytes D, C, B Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X
Truth Table for Read/Write[5, 9, 10]
Function (CY7C1442AV33) Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write Bytes B, A Write All Bytes Write All Bytes GW H H H H H H L BWE H L L L L L X BWB X H H L L L X BWA X H L H L L X
Notes: 9. BWx represents any byte write signal. To enable any byte write BWx, a Logic LOW signal should be applied at clock rise.Any number of bye writes can be enabled at the same time for any given write. 10. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05383 Rev. *B
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PRELIMINARY
Truth Table for Read/Write[5, 9, 10]
Function ( CY7C1446AV33) Read Read Write Byte x - (DQx and DQPx) Write All Bytes Write All Bytes GW H H H H L Test Access Port (TAP) Test Clock (TCK)
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
BWE H L L L X
BWx X All BW = H L All BW = L X
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 incorporates a serial boundary scan test access port (TAP). This part is fully compliant with IEEE Standard 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO)
TAP Controller State Diagram
1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1
The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document #: 38-05383 Rev. *B
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PRELIMINARY
TAP Controller Block Diagram
0 Bypass Register
210
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview
TDI
Selection Circuitry
Instruction Register
31 30 29 . . . 2 1 0
Selection
Circuitry
TDO
Identification Register
x. . . . .210
Boundary Scan Register
TCK TMS TAP CONTROLLER
Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR Document #: 38-05383 Rev. *B
Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the "Update IR" state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal
Page 12 of 27
PRELIMINARY
while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required--that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at , bit #89 (for 165-FBGA package) or bit #138 (for 209-fBGA package). When this scan cell, called the "extest output bus tristate", is latched into the preload register during the "Update-DR" state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the "Shift-DR" state. During "Update-DR", the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the "Test-Logic-Reset" state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
TAP Timing
1 Test Clock (TCK)
t TMSS
2
3
4
5
6
t TH t TMSH
t TL
t CYC
Test Mode Select (TMS)
t TDIS t TDIH
Test Data-In (TDI)
t TDOV t TDOX
Test Data-Out (TDO) DON'T CARE UNDEFINED
Document #: 38-05383 Rev. *B
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PRELIMINARY
TAP AC Switching Characteristics Over the operating Range[11, 12]
Parameter Clock tTCYC tTF tTH tTL tTDOV tTDOX tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise 0 5 5 5 25 25 50 Description Min.
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
Max.
Unit ns
20
MHz ns ns
Output Times 5 ns ns ns ns ns ns ns ns
Set-up Times
3.3V TAP AC Test Conditions
Input pulse levels ............................................... VSS to 3.3V Input rise and fall times ...................... ..............................1ns Input timing reference levels ...........................................1.5V Output reference levels...................................................1.5V Test load termination supply voltage...............................1.5V
2.5V TAP AC Test Conditions
Input pulse levels................................................ .VSS to 2.5V Input rise and fall time .....................................................1 ns Input timing reference levels................... ......................1.25V Output reference levels .................. ..............................1.25V Test load termination supply voltage .................... ........1.25V
3.3V TAP AC Output Load Equivalent
1.5V 50 TDO Z O= 50 20pF
2.5V TAP AC Output Load Equivalent
1.25V 50 TDO Z O= 50 20pF
Notes: 11. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 12. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = ns.
Document #: 38-05383 Rev. *B
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PRELIMINARY
TAP DC Electrical Characteristics And Operating Conditions
(0C < TA < +70C; VDD = 3.135 to 3.6V unless otherwise noted)[13] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND < VIN < VDDQ Test Conditions IOH = -4.0 mA, VDDQ = 3.3V IOH = -1.0 mA, VDDQ = 2.5V IOH = -100 A IOL = 8.0 mA IOL = 1.0 mA IOL = 100 A VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V 2.0 1.7 -0.3 -0.3 -5 Min. 2.4 2.0 2.9 2.1
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
Max.
Unit V V V V
0.4 0.4 0.2 0.2 VDD + 0.3 VDD + 0.3 0.8 0.7 5
V V V V V V V V A
Identification Register Definitions
Instruction Field Revision Number (31:29) Device Depth (28:24)[14] Architecture/Memory Type(23:18) Bus Width/Density(17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) CY7C1440AV33 (1 Mbit x 36) 000 01011 000000 100111 00000110100 1 CY7C1442AV33 (2 Mbit x 18) 000 01011 000000 010111 00000110100 1 CY7C1446AV33 (512K x 72) 000 01011 000000 110111 00000110100 1 Description Describes the version number. Reserved for Internal Use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor. Indicates the presence of an ID register.
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Order-165FBGA Boundary Scan Order-209fBGA Bit Size (x36) 3 1 32 89 - Bit Size (x18) 3 1 32 89 - Bit Size (x72) 3 1 32 - 138
Identification Codes
Instruction EXTEST IDCODE SAMPLE Z RESERVED Code 000 001 010 011 Captures the I/O ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Description
Notes: 13. All voltages referenced to VSS (GND). 14. Bit #24 is "1" in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05383 Rev. *B
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PRELIMINARY
Identification Codes (continued)
Instruction SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 100 101 110 111 Description
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
165-Ball fBGA Boundary Scan Order [15,16]
CY7C1440AV33 (1 Mbit x 36),CY7C1442AV33 (2 Mbit x 18) BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 BALL ID N6 N7 N10 P11 P8 R8 R9 P9 P10 R10 R11 H11 N11 M11 L11 K11 J11 M10 L10 K10 J10 H9 H10 BIT# 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 BALL ID B5 A5 A4 B4 B3 A3 A2 B2 C2 B1 A1 C1 D1 E1 F1 G1 D2 E2 F2 G2 H1 H3 J1
165-Ball fBGA Boundary Scan Order (continued)[15,16]
CY7C1440AV33 (1 Mbit x 36),CY7C1442AV33 (2 Mbit x 18) BIT# 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 BALL ID G11 F11 E11 D11 G10 F10 E10 D10 C11 A11 B11 A10 B10 A9 B9 C10 A8 B8 A7 B7 B6 A6 BIT# 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 BALL ID K1 L1 M1 J2 K2 L2 M2 N1 N2 P1 R1 R2 P3 R3 P2 R4 P4 N5 P6 R6 Internal
Notes: 15. Balls that are NC (No Connect) are preset LOW. 16. Bit# 89 is preset HIGH.
Document #: 38-05383 Rev. *B
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PRELIMINARY
209-Ball fBGA Boundary Scan Order
BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 BALL ID W6 V6 U6 W7 V7 U7 T7 V8 U8 T8 V9 U9 P6 W11 W10 V11 V10 U11 U10 T11 T10 R11 R10 P11 P10 N11 N10 M11 M10 L11 L10 K11 M6 L6 J6 BIT# 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
[15,17]
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
209-Ball fBGA Boundary Scan Order (continued) [15,17]
CY7C1446AV33 (512K x 72) BIT# 36 37 38 39 40 41 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 BALL ID F6 K8 K9 K10 J11 J10 C3 B3 A3 A2 A1 B2 B1 C2 C1 D2 D1 E1 E2 F2 F1 G1 G2 H2 H1 J2 J1 K1 N6 K3 K4 K6 K2 L2 BIT# 77 78 79 80 81 82 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 BALL ID C5 D5 D4 C4 A4 B4 L1 M2 M1 N2 N1 P2 P1 R2 R1 T2 T1 U2 U1 V2 V1 W2 W1 T6 U3 V3 T4 T5 U4 V4 5W 5V 5U Internal
CY7C1446AV33 (512K x 72) BALL ID H11 H10 G11 G10 F11 F10 E10 E11 D11 D10 C11 C10 B11 B10 A11 A10 C9 B9 A9 D7 C8 B8 A8 D8 C7 B7 A7 D6 G6 H6 C6 B6 A6 A5 B5
Note: 17. Bit# 138 is preset HIGH.
Document #: 38-05383 Rev. *B
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PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.3V to +4.6V DC Voltage Applied to Outputs in Tri-State........................................... -0.5V to VDDQ + 0.5V DC Input Voltage....................................-0.5V to VDD + 0.5V
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VDD VDDQ
3.3V - 5%/+10% 2.5V - 5% to VDD
Electrical Characteristics Over the Operating Range[18, 19]
Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[18] Input LOW Voltage[18] Input Load Current except ZZ and MODE VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V, VDD = Min., IOH = -4.0 mA VDDQ = 2.5V, VDD = Min., IOH = -1.0 mA VDDQ = 3.3V, VDD = Max.., IOL = 8.0 mA VDDQ = 2.5V, VDD = Max.., IOL = 1.0 mA VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V GND VI VDDQ 2.0 1.7 -0.3 -0.3 -5 -5 30 -30 5 -5 4.0-ns cycle, 250 MHz 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz ISB1 Automatic CE Power-down Current--TTL Inputs VDD = Max, Device Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC 4.0-ns cycle, 250 MHz 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz All speeds 5 475 425 375 225 225 225 100 Test Conditions Min. 3.135 3.135 2.375 2.4 2.0 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Max. 3.6 VDD 2.625 Unit V V V V V V V V V V V A A A A A A mA mA mA mA mA mA mA
Input Current of MODE Input = VSS Input = VDD Input Current of ZZ IOZ IDD Input = VSS Input = VDD Output Leakage Current GND VI VDDQ, Output Disabled VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC
ISB2
Automatic CE VDD = Max, Device Deselected, Power-down VIN 0.3V or VIN > VDDQ - 0.3V, Current--CMOS Inputs f = 0
ISB3
Automatic CE VDD = Max, Device Deselected, or 4.0-ns cycle, 250 MHz Power-down VIN 0.3V or VIN > VDDQ - 0.3V 5.0-ns cycle, 200 MHz Current--CMOS Inputs f = fMAX = 1/tCYC 6.0-ns cycle, 167 MHz Automatic CE Power-down Current--TTL Inputs VDD = Max, Device Deselected, VIN VIH or VIN VIL, f = 0 All speeds
200 200 200 110
mA mA mA mA
ISB4
Shaded areas contain advance information. Notes: 18. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 19. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD\
Document #: 38-05383 Rev. *B
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PRELIMINARY
Thermal Resistance[20]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 100 TQFP Package 25.21 2.28
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
165 BGA Package 20.8 3.2
209 fBGA Package 25.31 4.48
Unit C/W C/W
Capacitance[20]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V. VDDQ = 2.5V 100 TQFP Package 6.5 3 5.5 165 BGA Package 5 5 7 209 fBGA Package 5 5 7 Unit pF pF pF
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50 5 pF R = 351 R = 317 ALL INPUT PULSES VDDQ 10% GND 1 ns 90% 90% 10% 1 ns
VT = 1.5V
(a) 2.5V I/O Test Load
OUTPUT Z0 = 50
INCLUDING JIG AND SCOPE 2.5V
(b)
R = 1667 VDDQ 10% GND R = 1538 1 ns
(c)
ALL INPUT PULSES 90% 90% 10% 1 ns
OUTPUT RL = 50 VT = 1.25V 5 pF INCLUDING JIG AND SCOPE
(a)
(b)
(c)
Switching Characteristics Over the Operating Range [25, 26]
250 MHz Parameter tPOWER Clock tCYC tCH tCL Output Times tCO tDOH tCLZ Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z[22, 23, 24] 1.0 1.0 2.6 1.5 1.3 3.2 1.5 1.5 3.4 ns ns ns Clock Cycle Time Clock HIGH Clock LOW 4.0 1.5 1.5 5 2.0 2.0 6 2.4 2.4 ns ns ns Description VDD(Typical) to the first Access[21] Min. 1 Max 200 MHz Min. 1 Max. 167 MHz Min. 1 Max Unit ms
Notes: 20. Tested initially and after any design or process change that may affect these parameters. 21. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 22. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 23. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions 24. This parameter is sampled and not 100% tested. 25. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 26. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05383 Rev. *B
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PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[25, 26]
250 MHz Parameter tCHZ tOEV tOELZ tOEHZ Set-up Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tADVH tWEH tDH tCEH Address Hold After CLK Rise ADSP, ADSC Hold After CLK Rise ADV Hold After CLK Rise GW, BWE, BWX Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.3 0.3 0.3 0.3 0.3 0.3 0.4 0.4 0.4 0.4 0.4 0.4 Address Set-up Before CLK Rise ADSC, ADSP Set-up Before CLK Rise ADV Set-up Before CLK Rise GW, BWE, BWX Set-up Before CLK Rise Data Input Set-up Before CLK Rise Chip Enable Set-up Before CLK Rise 1.2 1.2 1.2 1.2 1.2 1.2 1.4 1.4 1.4 1.4 1.4 1.4 Clock to High-Z Description
[22, 23, 24]
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
200 MHz Min. Max. 3.0 3.0 0
167 MHz Min. Max 3.4 3.4 0 3.4 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min.
Max 2.6 2.6
OE LOW to Output Valid OE LOW to Output Low-Z
[22, 23, 24]
0 2.6
OE HIGH to Output High-Z[22, 23, 24]
3.0
Shaded areas contain advance information.
Document #: 38-05383 Rev. *B
Page 20 of 27
PRELIMINARY
Switching Waveforms
Read Cycle Timing[27]
t CYC
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
CLK t CH t ADS ADSP tADS ADSC tAS A1 tWES GW, BWE, BWx tCES CE tADVS tADVH ADV ADV suspends burst. OE tOEV t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t CO Burst wraps around to its initial state Single READ BURST READ t OELZ tCO tDOH Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) t CHZ Q(A2 + 1) tCEH Deselect cycle tWEH tAH tADH t ADH t CL
ADDRESS
A2
A3 Burst continued with new base address
DON'T CARE
UNDEFINED
Note: 27. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05383 Rev. *B
Page 21 of 27
PRELIMINARY
Switching Waveforms (continued)
Write Cycle Timing[27, 28]
t CYC
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
CLK tCH tADS ADSP ADSC extends burst tADS tADH tADH tCL
tADS ADSC tAS A1 tAH
tADH
ADDRESS
A2 Byte write signals are ignored for first cycle when ADSP initiates burst
A3
tWES tWEH
BWE, BWX tWES tWEH GW tCES CE t t ADVS ADVH ADV ADV suspends burst tCEH
OE tDS tDH
Data In (D)
High-Z
t OEHZ
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE
DON'T CARE
UNDEFINED
Note: 28. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document #: 38-05383 Rev. *B
Page 22 of 27
PRELIMINARY
Switching Waveforms (continued)
Read/Write Cycle Timing[27, 29, 30]
tCYC
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
CLK tCH tADS ADSP tADH tCL
ADSC tAS tAH
ADDRESS
A1
A2
A3 tWES tWEH
A4
A5
A6
BWE, BWX tCES CE tCEH
ADV
OE tCO tDS tDH tOELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ Q(A2) Single WRITE D(A3) D(A5) D(A6)
Q(A4)
Q(A4+1) BURST READ
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
DON'T CARE
UNDEFINED
Notes: 29. The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC. 30. GW is HIGH.
Document #: 38-05383 Rev. *B
Page 23 of 27
PRELIMINARY
Switching Waveforms (continued)
ZZ Mode Timing[32, 33]
CLK
t ZZ t ZZREC
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Ordering Information
Speed (MHz) 250 Ordering Code CY7C1440AV33-250AXC CY7C1442AV33-250AXC CY7C1440AV33-250BZC CY7C1442AV33-250BZC CY7C1446AV33-250BGC CY7C1440AV33-250BZXC CY7C1442AV33-250BZXC CY7C1446AV33-250BGXC 200 CY7C1440AV33-200AXC CY7C1442AV33-200AXC CY7C1440AV33-200BZC CY7C1442AV33-200BZC CY7C1446AV33-200BGC CY7C1440AV33-200BZXC CY7C1442AV33-200BZXC CY7C1446AV33-200BGXC BB209A 209-ball Ball Grid Array (14 x 22 x 1.76 mm) BB165C Lead-Free 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) BB209A Lead-Free 209-ball Ball Grid Array (14 x 22 x 1.76 mm) Package Name A101 Part and Package Type Lead-Free 100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Operating Range Commercial
BB165C 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) BB209A 209-ball Ball Grid Array (14 x 22 x 1.76 mm) BB165C Lead-Free 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) BB209A Lead-Free 209-ball Ball Grid Array (14 x 22 x 1.76 mm) A101 Lead-Free 100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
BB165C 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. 32. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 33. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05383 Rev. *B
Page 24 of 27
PRELIMINARY
Ordering Information (continued)
Speed (MHz) 167 Ordering Code CY7C1440AV33-167AXC CY7C1442AV33-167AXC CY7C1440AV33-167BZC CY7C1442AV33-167BZC CY7C1446AV33-167BGC CY7C1440AV33-167BZXC CY7C1442AV33-167BZXC CY7C1446AV33-167BGXC Package Name A101 Part and Package Type
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
Operating Range Commercial
Lead-Free 100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
BB165C 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) BB209A 209-ball Ball Grid Array (14 x 22 x 1.76 mm) BB165C Lead-Free165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) BB209A Lead-Free 209-ball Ball Grid Array (14 x 22 x 1.76 mm)
Package Diagrams
165-Ball FBGA (15 x 17 x 1.40 mm) BB165C
BOTTOM VIEW TOP VIEW O0.05 M C PIN 1 CORNER O0.25 M C A B O0.450.05(165X)
1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1
PIN 1 CORNER
A B
A B
D E F G
1.00
C
C D E F G
17.000.10
H J K
14.00
H J K
M N P R
7.00
L
L M N P R
A 5.00 10.00 0.530.05 0.25 C
+0.05 -0.10
1.00
0.35
0.15 C
B 0.15(4X)
15.000.10
SEATING PLANE C 0.36 1.40 MAX.
51-85165-*A
Document #: 38-05383 Rev. *B
Page 25 of 27
PRELIMINARY
Package Diagrams (continued)
209-Ball FBGA (14 x 22 x 1.76 mm) BB209A
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
51-85167-**
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05383 Rev. *B
Page 26 of 27
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
Document History Page
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33
Document Title: CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Document Number: 38-05383 REV. ** *A ECN NO. 124437 254910 Issue Date 03/04/03 See ECN Orig. of Change CJM SYT New data sheet Part number changed from previous revision. New and old part number differ by the letter "A" Modified Functional Block diagrams Modified switching waveforms Added Boundary scan information Added Footnote #14 (32-Bit Vendor ID Code changed) Added IDD, IX and ISB values in the DC Electrical Characteristics Added tPOWER specifications in Switching Characteristics table Removed 119 PBGA package Changed 165 FBGA package from BB165C (15 x 17 x 1.20 mm) to BB165 (15 x 17 x 1.40 mm) Changed 209-Lead PBGA BG209 (14 x 22 x 2.20 mm) to BB209A (14 x 22 x 1.76 mm) Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA on Page # 6 Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 Mhz speed bin on the Switching Characteristics table on Page # 19 Changed JA and JC from TBD to 25.21 and 2.58 C/W respectively for TQFP Package on Pg # 19 Replaced JA and JC from TBD to respective Values for 165 BGA and 209 fBGA Packages on the Thermal Resistance Table Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 fBGA Packages . Changed IDD from 450, 400 and 350 mA to 475, 425 and 375 mA for frequencies of 250, 200 and 167 MHz respectively Changed ISB1 from 190, 180 and 170 mA to 225 mA for frequencies of 250, 200 and 167 MHz respectively Changed ISB2 from 80 to 100 mA Changed ISB3 from 180, 170 and 160 mA to 200 mA for frequencies of 250, 200 and 167 MHz respectively Changed ISB4 from 100 to 110 mA Description of Change
*B
306335
See ECN
SYT
Document #: 38-05383 Rev. *B
Page 27 of 27

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